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The chapter concludes with a proposed software radio design flow with special emphasis on the RF stages. Chapter 4: Analog-to-Digital and Digital-to-Analog Conversion Arguably the most critical function in a wideband software radio, we investigate the analog-to-digital conversion ADC and digital-to-analog conversion DAC performance requirements needed for 3G cellular systems. Performance parameters such as SFDR, dynamic range, and jitter are introduced. A figure of merit FOM for software radio applications is provided as an initial guide when selecting a converter from the large range of commercially available options.
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Chapter 5: Digital Frequency Up- and Downconverters For wireless systems operating above the 20—MHz range, digital frequency up and downconverters are currently the most efficient bridge between digital intermediate frequencies and baseband processors. Figures illustrating the 3G performance for these converters are also included. Chapter 6: Signal Processing Hardware Components An important goal for 3G software radio is to perform all symbol and chiprate processing in software.
This chapter commences with an analysis of the required signal processing power for UMTS and introduces the major CDMA layer one processing functions—for example, path searching and rake receivers. The chapter concludes with symbol and chip-rate partitioning. Chapter 7: Software Architecture and Components Reconfiguring the radio with software is the most important requirement, and this chapter starts by discussing the ideas of hardware abstraction and then proceeds with details of the software architectural proposals produced xviii Software Defined Radio for 3G by the JTRS JPO and the SDRF.
These specifications use object-oriented design principles; the chapter includes many UML figures to explain the designs. Chapter 8: Applications for Wireless Systems To design an efficient and cost-effective 3G software radio it is necessary to have a depth of understanding that extends from the wireless network components e. This chapter commences by explaining the fundamental concepts behind CDMA transmission and reception and covers the rake receiver in more detail, as well as introducing the concepts of handover and power control.
A major part of the chapter is devoted to several example software radio implementations, with details of the software and hardware architectures. The chapter concludes with details of an example 3G network in Korea, including statistics about the number of base stations, network coverage, and so on. Chapter 9: Smart Antennas Using Software Radio Software defined radio is an enabling technology, and smart antennas are one of the ideal applications. Architectures for implementing smart antennas on a software radio platform are introduced.
There are many classes of candidate algorithms e. The chapter concludes with a block diagram of a flexible hardware architecture suitable for implementing smart antenna software. Preface xix Chapter Low-Cost Experimental Software Radio Platform This chapter puts the theory of previous chapters into practice and provides the outline of a design for an experimental, low-cost software radio platform that can be purchased off-the-shelf. The platform has the capability to teach the fundamentals of software radio and is ideal for university labs and smallscale development.
Software can be developed in C and makes use of a DSP operating system if required. The importance of memory management and FIFO buffers is stressed; sampling rate issues are covered, as well as many of the implementation-level details, including register settings. Chapter Engineering Design Assistance Tools The complexity of current digital radio air interfaces almost mandates the use of engineering design assistance EDA tools during the development of new products; this applies equally well to software and hardware implementations.
This chapter explores the benefits of EDA tools and reviews several popular tools well suited to software radio and 3G cellular systems development.
I hope you find this book helpful and that after reading the work you will be enthused enough to contribute to the advancement of this fantastic technology. Software defined radio SDR is growing in popularity and the expression is becoming recognized in the wider technical community. Most radios are hardware defined with little or no software control; they are fixed in function for mostly consumer items for broadcast reception.
They have a short life and are designed to be discarded and replaced. Software defined radio uses programmable digital devices to perform the signal processing necessary to transmit and receive baseband information at radio frequency. Devices such as digital signal processors DSPs and field programmable gate arrays FPGAs use software to provide them with the required signal processing functionality. This technology offers greater flexibility and potentially longer product life, since the radio can be upgraded very cost effectively with software.
A major challenge for software defined radio is to equal the efficiencies of purely hardware solutions while providing the flexibility and intelligence that software can offer. Efficiencies can be measured by the cost per informa1 2 Software Defined Radio for 3G tion bit; the power consumed per information bit, and the physical volume consumed per information bit.
Also, the user will not need or want to know the underlying technology of the radio but will still demand higher efficiency, more flexibility, and greater intelligence. At the same time the software radio applications developer will want to be shielded from the details of the computing and signal processing hardware and complete all development in a unified environment using a single high-level language. The latest explosion in radio communications caused by the cellular mobile phone is a prime contributor to the effort being invested in SDR.
Combined with a seemingly endless exponential growth in silicon chip computing power, the twenty-first century is sure to see radio communications expand and software radio play an increasingly significant role. The digital nature of 2G allows limited fixed rate data services. This standard includes such provisions as the ability to support up to 2 Mbps data connections. Some see 3G as a means to provide new services to customers, while others see the next generation as purely a means of providing much needed capacity via better spectrum utilization. An important problem with 3G is that it has added to the number of air interface standards that needs to be supported by the infrastructure and terminal industry.
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All of the 3G systems are potential SDR applications. Software radio offers the potential to solve many of the problems caused by the proliferation of new air interfaces. Intelligent SDRs can detect the local air interface and adapt to suit the need; this capability will be valuable for frequent intercountry travelers. Figure 1. This design has been around since the s and it is almost certain that a majority of homes would possess a superheterodyne receiver of some sort broadcast radio, television, and so on.
From the receiver point of view the RF from the antenna is converted down to an intermediate frequency by mixing or multiplying the incoming signal with the first local oscillator, LO1. The IF is filtered and then mixed down to baseband by the second oscillator, LO2, and mixer. The baseband modulated signal is demodulated to produce the analog receive information, and the reciprocal functions are performed for the transmitter. The number of conversion stages is dependent upon the RF operating frequency, and theoretically it is possible to add stages and push the operating frequency higher.
The analog superheterodyne radio has experienced a marvelously successful history; it was used in 1G mobile phone terminals and is sure to endure in lowcost broadcast radio receivers for many years to come.
This architecture was suited to 1G mobile phone systems, such as advanced mobile phone system AMPS , which used frequency modulation FM and frequency division multiplexing FD to allow multiple users to access a fixed piece of spectrum. The analog functions are restricted to those that cannot be performed digitally—that is, antenna, RF filtering, RF combination, receive preamplification, transmit power amplification and reference frequency generation.
The architecture pushes the analog conversion stage right up as close as possible to the antenna, in this case prior to the power amplifier PA in the transmitter and after the low noise amplifier LNA in the receiver. Similarly, the channel coding and modulation functions are performed digitally at baseband by the same processing resources.
Software for the ideal architecture is layered so that the hardware is completely abstracted away from the application software. A middleware layer achieves this functionality by wrapping up the hardware elements into objects and providing services that allow the objects to communicate with Figure 1. Middleware includes the operating system, hardware drivers, resource management, and other non-application-specific software. The combination of hardware and middleware is often termed a framework.
Future SDR designs and frameworks that use an open API into the middleware will make applications development more portable,quicker,and cheaper. Applications developers will be freed from designing ways to program the low-level hardware and allowed to concentrate on building more complicated and powerful applications. The ideal architecture is commercially feasible for limited low data rate HF and VHF radios but is not yet practical for any generation of cellular mobile phone technology. The ideal architecture is useful as a point of comparison and acts as a guide for the development of hardware and middleware in the future.
Practical architectures for cellular radio are covered in Chapters 2 and 8.
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DSP chip designers in the s realized that general-purpose computing architectures e. Microcontrollers extensively use the Von Neumann memory architecture, as shown in Figure 1.
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The single data bus causes a bottleneck in the system by only allowing either new instructions or data to be fetched from external memory and loaded into the CPU. Many DSP chips avoid the instruction and data contention by employing the Harvard architecture, as shown in Figure 1. By using two address buses and two data buses, each connected to its own piece of external memory, it is possible for new instructions to be fetched at the same time as new data. This allows for effective pipelining, where instructions for the next series of data can be loaded at the same time as operations are performed on the current set of data.
General-purpose processors without a dedicated multiplier require many shift and add operations to achieve the same result, consuming precious clock cycles.